The present invention relates generally to the fabrication of interconnect structures on a semiconductor device. More specifically, the invention relates to interconnect structures incorporating low-k and ultra low-k dielectric materials, and dual damascene processes used in the fabrication of interconnect structures.
Interconnect structures are those structures on an integrated circuit device that connect different levels of a multi-level-interconnect integrated circuit device. An interconnect structure includes an upper and lower conductive metal layer separated by a dielectric layer. The conductive metal layers comprise metal lines spaced apart within a dielectric material. Conductive metal-filled vias interconnect the metal lines of the upper metal layer to the conductive lines of the lower metal layer. Typically, in a multi-level structure, the lowest metal layer is fabricated using a process known as single damascene, and the dielectric layers and upper metal layers are fabricated using a process known as dual damascene. These damascene processes are known to those skilled in the art.
Dielectric materials have relatively low conductivity and high resistivity to movement of electrons, and accordingly serve as insulators to the conductive metal structures in a semiconductor device. Interconnect delay can be reduced by decreasing the resistance of a metal layer and decreasing the capacitance of the dielectric layers. Dielectric materials having smaller permittivity values, or lower dielectric constants, reduce the capacitance of the structure. The dielectric materials separate adjacent metal lines and vias, thereby preventing shorting between the metal layers and conductive lines on the same layer. Moreover, dielectric layers are also used to separate conductive metal layers at different levels of an interconnect structure.
However, as the dimensions of semiconductor devices decrease, the overall capacitance of a device may increase. Spacing between conductive lines on the same metal layer is decreased which can increase the potential of intra-level capacitance. Similarly, if the thickness of a dielectric layer between various metal layers is decreased, the inter-level capacitance of the device structure may increase.
As a result of these decreasing dimensions of devices, dielectric materials having lower dielectric constants, known as low-k dielectric materials, have become increasingly popular in the fabrication of interconnect structures of semiconductor devices. The low-k dielectric materials typically have dielectric constants of up to about 4.0. These dielectric materials are typically organosilicates or polymeric materials. Low-k dielectric materials provide a lower intra-level and inter-level capacitance.
In addition, dielectric materials known as “ultra low-k” dielectrics have been found to further reduce the capacitance of an interconnect layer. Ultra low-k dielectrics include materials such as xerogel, aerogel and other materials having a dielectric constant of up to about 2.5. Ultra low-k dielectric materials are generally porous, brittle and lack structural integrity to support other device layers and films comprising a semiconductor device. For examples barrier/seed films do not adhere well to ultra-low k dielectrics. A barrier/seed film may peel off during metal deposition or subsequent chemical mechanical planarization of copper, and create particulates that limit device yield and performance. In addition, the porous ultra-low k materials can create uneven surfaces of the barrier/seed films, which can compromise the barrier integrity. In a worst case, gross delamination of the films may occur, producing a non-functioning device.
The use of an ultra low-k dielectric material in combination with a low-k dielectric, to reduce the capacitance of a semiconductor device, is disclosed in U.S. Pat. No. 6,159,842, issued to Chang. A conductive layer having lines 14 are formed by a subtractive etch process. A low-k dielectric material, having a dielectric constant of up to about 3.5, is deposited over the lines 14 to protect the lines 14 from an ultra low-k material deposited later. The ultra-low k dielectric material 18 is then deposited over the low-k insulating layer 16 to fill gaps between the lines 14. The top surface of layer 18 is densified by plasma treatment, and a second insulating layer 20 is deposited over the lines 14 and ultra low-k dielectric 18. The second insulating layer 20 is composed of a low-k dielectric material similar to the insulating layer 16. The Chang patent does not disclose the fabrication of the interconnect structure using a dual damascene process, and does not include the ultra low-k dielectric material between the metal-filled vias.
A dual damascene process of an interconnect structure designed to lower inter-level device capacitance is disclosed in U.S. Pat. No. 6,297,554, issued to Lin. However, Lin does not utilize an ultra low-k dielectric material. Lin creates voids in the low-k dielectric layer between adjacent metal structures which maybe difficult to achieve, and may compromise the structural integrity of the device. A CMP stopping point may be difficult to repeat from device to device without exposing the voids. In addition, slurry chemicals used in CMP can become entrapped within the voids, which will affect the function of voids. The voids are also difficult to reproduce without preventing overhang of the barrier and seed layers which leads to poor fill of interconnect metal features.